Method to increase capacitance

ABSTRACT

A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon. A second layer of polysilicon is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer left by the etching stop. A capacitor dielectric is formed over the second layer of polysilicon and then an upper capacitor electrode is provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the formation of capacitors forintegrated circuit memories and particularly to methods of forming highcapacitance structures in a high production volume manufacturingenvironment.

2. Description of the Related Art

In dynamic random access memories (DRAMs), information is typicallystored by selectively charging or discharging each capacitor of an arrayof capacitors formed on the surface of a semiconductor substrate. Mostoften, a single bit of binary information is stored at each capacitor byassociating a discharged capacitor state with a logical zero and acharged capacitor state with a logical one, or vice versa. The surfacearea of the electrodes of the memory capacitors determines the amount ofcharge that can be stored on each of the capacitors for a givenoperating voltage, for the electrode separation that can reliably bemanufactured, and for the dielectric constant of the capacitordielectric used between the electrodes of the charge storage capacitor.Read and write operations are performed in the memory by selectivelycoupling the charge storage capacitor to a bit line to either transfercharge to or from the charge storage capacitor. The selective couplingof the charge storage capacitor to the bit line is typicallyaccomplished using a transfer field effect transistor (FET). The bitline contact is typically made to one of the source/drain electrodes ofthe transfer FET and the charge storage capacitor is typically formed incontact with the other of the source/drain electrodes of the transferFET. Word line signals are supplied to the gate of the FET to connectone electrode of the charge storage capacitor through the transfer FETto the bit line contact facilitating the transfer of charge between thecharge storage capacitor and the bit line.

There is a continuing trend toward increasing the storage density ofintegrated circuit memories to provide increased quantities of datastorage on a single chip. Higher density memories provide storage thatis generally more compact and is often cheaper on a per bit basis thanan equivalent amount of storage provided on plural chips. It hasgenerally been possible to provide these higher levels of storage atequivalent or improved levels of performance as compared to the earlier,less dense memory chips. Historically, the density of integrated circuitdevices has been increased in part by decreasing the size of structuressuch as wiring lines and transistor gates and in part by decreasing theseparation between the structures that make up the integrated circuitdevice. Reducing the size of circuit structures is generally referred toas decreasing the "design rules" used for the manufacture of theintegrated circuit device.

Applying reduced design rules to a DRAM reduces the substrate surfacearea that can be devoted to the charge storage capacitor of the DRAM.Thus, applying reduced design rules to conventional planar capacitordesigns reduces the amount of charge (i.e., capacitance) that can bestored on the charge storage capacitor. Reducing the amount of charge onthe capacitor leads to a variety of problems, including the potentialloss of data due to greater susceptibility to decay mechanisms and tocharge leakage. This greater susceptibility to charge loss may cause theDRAM to require more frequent refresh cycles, which are undesirablesince the memory may be unavailable for data storage and readouttransactions during refresh activities. In addition, reduced levels ofcharge storage might require more sophisticated data readout schemes ormore sensitive charge sensing amplifiers. Thus, modem DRAMs requireincreased levels of capacitance in reduced substrate area DRAM cells. Tothis end, a variety of very complex capacitor structures having threedimensional charge storage surfaces have been proposed. In general,these complex capacitor structures are difficult to manufacture. This isparticularly true when the requirements are taken into account forforming such capacitor structures in a high throughput manufacturingenvironment in a manner compatible with high yields.

One strategy that has been adopted in attempting to improve the DRAMcell capacitance has been to incorporate hemispherical grainedpolysilicon within the charge storage capacitor. Most current DRAMcapacitor designs incorporate conventional polysilicon within bothelectrodes of the capacitor. While the conventional polysilicon can beshaped into very complex shapes, its surface is essentially smooth.Hemispherical grained polysilicon (HSG-Si) is a particular form ofpolysilicon that has a rough surface when deposited under carefullycontrolled conditions and which can be incorporated on the surface ofthe capacitor electrode to increase the surface area of the electrode.By providing a layer of hemispherical grained polysilicon on onecapacitor electrode, the capacitance of a given DRAM charge storagecapacitor can be increased by a factor of approximately 1.8 times.

There are, on the other hand, disadvantages to the use of HSG-Si in DRAMcapacitors. HSG-Si can have unpredictable surface properties that canreduce capacitance or reduce the stability of the capacitor. Inaddition, it can be difficult to adequately dope HSG-Si duringdeposition. Thus, in addition to the precise control required in thedeposition process, it is typically necessary to include a separatedoping step to ensure that the HSG-Si layer has an appropriate level ofconductivity for use on the surface of the capacitor electrode. Theprocessing difficulty associated with using HSG-Si on the surface of apolysilicon capacitor electrode limits is applicability to high volumemanufacturing processes. In many instances, the gain in capacitanceachieved through use of HSG-Si in a capacitor does not justify the addedexpense and reduced yields associated with its use.

It is an object of the present invention to provide increased levels ofcharge storage capacitance for an integrated circuit capacitor of thetype that might be used in a memory. It is a further object of thepresent invention to provide increased capacitance in a highlymanufacturable manner.

SUMMARY OF THE PREFERRED EMBODIMENTS

According to one aspect, the present invention provides increasedcapacitance to a charge storage structure in an integrated circuit thathas an access circuit for controlling access to the charge storagestructure through an electrode contact. A first conductive layer isprovided over the substrate and a layer of dielectric material isprovided over the first conductive layer. A layer consisting of grainsof polysilicon is provided over the surface of the layer of dielectricmaterial so as to leave uncovered portions of the surface of the layerof dielectric layer between the grains of polysilicon. Exposed portionsof the layer of dielectric material are selectively removed to formspaced apart columns of dielectric material extending above the firstconductive layer. A second conductive layer is provided over the columnsof dielectric material. A capacitor dielectric layer is provided overthe second conductive layer. A third conductive layer is then providedover the capacitor dielectric layer.

Another aspect of the present invention provides increased capacitanceto a charge storage capacitor connected to a field effect transistorhaving a source/drain region formed on a substrate. A first dielectriclayer is provided over the field effect transistor and a contact via isformed to expose the source/drain region. A first polysilicon layer isprovided over the first dielectric layer which is electrically connectedto the source/drain region. A second dielectric layer is provided overthe first polysilicon layer and a layer of hemispherical grainedpolysilicon is provided over the second dielectric layer. Portions ofthe second dielectric layer are exposed between grains of the layer ofhemispherical grained polysilicon. Anisotropic etching removes thesecond dielectric layer to expose a portion of the first polysiliconlayer in a pattern defined by the grains of the layer of hemisphericalgrained polysillicon. Structures etched from the second dielectric layerextend above the first polysilicon layer. A second polysilicon layer isdeposited over the exposed pattern of the first polysilicon layer andover the structures etched from the second dielectric layer. A thirddielectric layer is provided over the second polysilicon layer and athird polysilicon layer is provided over the third dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-7 illustrate steps in the manufacture of a DRAM in accordancewith preferred aspects of the present invention.

FIG. 8 illustrates another configuration of DRAM formed in accordancewith the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention provide a highcapacitance DRAM capacitor using methods compatible with high volumemanufacture. In accordance with a particularly preferred embodiment ofthe present invention, a transfer FET is formed for the DRAM cell in andon a substrate along with the wiring lines and other portions of theaccess circuitry for the DRAM cell. The lower electrode of the chargestorage capacitor is formed in a several stage process. A first layer ofpolysilicon is deposited in contact with one of the source/drain regionsof the transfer FET and then a layer of silicon oxide is deposited onthe first layer of polysilicon. Hemispherical grained polysilicon(HSG-Si) is formed on the surface of the silicon oxide layer so that thegrains are relatively sparsely distributed over the surface. The grainsof HSG-Si are used as a mask to selectively etch the oxide layer,preferably stopping on the first layer of polysilicon, with the firstlayer functioning as an etch stop for the etching process. A secondlayer of polysilicon is deposited over the grains of HSG-Si, over theremaining, column-shaped portions of the oxide layer and in contact withthe first layer of polysilicon to provide a surface for the lowercapacitor electrode. The second layer of polysilicon is renderedconductive, preferably by in situ doping during deposition. A capacitordielectric layer and an upper capacitor electrode are provided tocomplete the DRAM capacitor.

Manufacture of a DRAM in this manner provides a device that has a highlevel of capacitance using a comparatively simple process. Features areprovided on the DRAM capacitor that are smaller than thephotolithography resolution limit because the vertically extendingportions of the bottom electrode are formed in an etching process thatuses a mask made up of grains of hemispherical grained polysilicon. Thelayer of hemispherical grained polysilicon has grain sizes on the orderof approximately 50-100 nanometers and individual grains are preferablyspaced apart by a distance on the order of 50-100 nanometers. The bottomcapacitor electrode formed about the insulating structures defined usingthe mask has structures with lateral dimensions much smaller than thelithography resolution limit presently available in commercial steppers.In addition, while this method is easily implemented for capacitorsbased on polysilicon electrodes, the method may also be implementedusing a variety of other conductors within the capacitor. Furtherdiscussion of these aspects and other preferred aspects of the presentinvention is now presented with specific reference to FIGS. 1-7.

Formation of a dynamic random access memory (DRAM) in accordance withpreferred embodiments of the present invention begins on a P-typesilicon substrate 10. FIG. 1 illustrates a substrate 10 having deviceisolation structures 12 formed on its surface and with a gate oxidelayer 14 covering the active device regions of the substrate. The deviceillustrated in FIG. 1 incorporates field oxide regions formed by thelocal oxidation of silicon (LOCOS) technique as device isolationstructures 12. Other types of device isolation regions might alternatelybe provided including, for example, shallow trench isolation regionsfilled with CVD oxide.

Transfer FETs are formed on the active device region in the conventionalfashion. Typically, a polysilicon layer is deposited over the substrateand patterned to define polysilicon gate electrodes 16 and wiring lines18. The polysilicon may be doped either in situ during deposition or byion implantation of the blanket deposited polysilicon layer beforepatterning or at some later point in processing. N-type source/drainregions are 20, 22 provided in the substrate 10 on either side of gateelectrode 16. In some embodiments, it may be preferred to provide alightly doped drain (LDD) structure for each of the source/drain regions20, 22 illustrated in FIG. 1.

Presently, however, it is more desirable to provide a uniformly dopedN-type region for each of the source/drain regions 20, 22.

It is typically preferred to provide protective dielectric layers aroundthe gate electrode 16 and the wiring line 18 to protect these conductorsduring subsequent processing and to reduce the possibility of undesiredcontacts being formed to the conductors 16, 18. Consequently, it istypical to provide oxide layers 24, 26 over the gate electrode 16 andwiring line 18, respectively. Typically, these oxide layers are providedover the blanket deposited polysilicon layer prior to the patterningsteps used to define the gate electrode 16 and wiring line 18.Alternately, silicon nitride or an oxynitride might be provided as acapping, protective dielectric layer over the gate electrode. It is alsodesirable to form protective dielectric layers on the sides of gateelectrode 16 and wiring line 18. In some cases oxide spacer structures28 are formed on the sides of gate electrode 16 and wiring line 18 inthe process of forming a lightly doped drain (LDD) structure for thesource/drain regions of the transfer FET. In those embodiments where anLDD structure is formed for the source/drain regions, the oxide spacerstructures are typically left in place during subsequent processing. Inthose presently preferred embodiments of the present invention in whicha constant doping is at least initially provided to the source/drainregions 20, 22, oxide spacer structures 28 are preferably formedalongside the gate electrode 16 and wiring line 18 to protect thoseconductors and to prevent shorts later in processing. Oxide spacerstructures 28 may be formed by providing a blanket oxide layer bychemical vapor deposition (CVD) to a thickness approximately equal tothe width desired for the oxide spacer structures 28. An anisotropicetchback process using, for example, an etchant derived from a plasmasource incorporating a CF₄ or other fluorine bearing species may be usedto form the illustrated oxide spacer structures 28.

After the transfer FET and wiring lines are defined, a layer of oxide 30is deposited over the FIG. 1 structure. Typically, the oxide layer isdeposited to a thickness of 1000-2000 Å by a chemical vapor deposition(CVD) process. The oxide layer 30 shown in FIG. 2 protects the circuitryformed on the FET, including the source/drain regions 20, 22, so thatinadvertent and unintended contacts are avoided throughout subsequentprocessing steps. The capacitor formation process begins by defining acontact via which exposes the source/drain region 22 of the transfer FETso that the bottom capacitor electrode can be formed in contact with thesource/drain region 22. To this end, a photoresist mask 32 is defined byconventional photolithography on oxide layer 30 so as to have an opening34 over the selected source/drain region 22. Etching is performedthrough the opening 34 to form a via through the oxide layer 30, forexample, using plasma etching with a fluorine etch chemistry.Preferably, this etching step stops on the substrate but still clearsthe source/drain region 22 so the bottom capacitor electrode can beformed partially on the source/drain region 22. The photoresist mask 32is stripped, preferably by ashing, leaving behind the unetched portionsof the oxide layer 30. The sidewalls 34 of the oxide layer 30 that faceon the contact via provide elevation and further structure for thebottom capacitor electrode to be formed in contact with the source/drainregion 22. Next, a layer of polysilicon 36 is deposited by low pressurechemical vapor deposition (LPCVD) to a thickness of approximately1500-2500 Å as shown in FIG. 3. This polysilicon layer 36 may be dopedN-type in situ during deposition or by a subsequent ion implantation andannealing step, as in known in the art. It is possible to use otherconductors as the plate on which the lower capacitor electrode isformed, so long as the material can be used as an etch stop forsubsequent etching steps.

Next, a layer of oxide 38 (FIG. 4) is deposited by blanket CVD over thepolysilicon layer 36 to a thickness of about 2000-3000 Å. The oxidelayer 38 will be formed into structures extending above the plate onwhich the lower capacitor electrode is formed. Although oxide is themost preferred material, these structures need not be oxide or aninsulating material if processes are available to make alternatematerials compatible with this method. The material used for layer 38 ischosen to be sufficiently different from the layer 36 and hemisphericalgrained polysilicon to allow the hemispherical grained polysilicon toact as a mask for etching the layer 38, using the layer 36 as an etchstop. Silicon oxide and other insulating materials are particularlypreferred for layer 38 because etchants are readily available thatselectively etch oxide and other insulators when using polysilicon as amask and as an etch stop.

A layer of hemispherical grained polysilicon (HSG-Si) 40 is formed overthe oxide layer 38 that will be used as a mask for etching the oxidelayer 38 to provide structures extending vertically from the surface ofpolysilicon layer 36. The HSG-Si layer 40 may be formed in any of thewell known methods and may consist of low pressure chemical vapordeposition of HSG-Si from a silane source gas onto a substrate held at atemperature of between 555° C. to 595° C. The resulting structureincludes an irregular surface of HSG-Si grains due to the largely randomnature of the nucleation of HSG-Si growth. Most preferably, the HSG-Silayer will have a sparse distribution of grains over the surface of theoxide layer 38. For example, the HSG-Si layer 40 may include grains thatvary in size from 50-100 nanometers in diameter that are spaced on theaverage approximately 50-150 nanometers apart. It is typicallyunnecessary to dope the HSG-Si layer 40 for the grains to be used in anetching mask. The HSG-Si layer 40 is then used as a mask for etching theoxide layer 38. The etching process may, for example, consist of plasmaetching using an etchant derived from either a CHF₃ or SF₆ source gas.The etched structure is shown in FIG. 6 and includes verticallyextending portions 42 defined from the oxide layer 38 in the etchingprocess.

In the preferred embodiments of the present invention which utilizeoxide or another insulator to form the structures 42 which extendvertically from the surface of the preferred polysilicon layer 36 to thegrains 40 of the HSG-Si mask, it is necessary to provide a conductivesurface over the structures 42 and, for most embodiments, over theundoped grains of HSG-Si. This is most easily accomplished by LPCVD of athin layer of polysilicon, preferably doped N-type in situ duringdeposition or by a subsequent diffusion step. This thin polysiliconlayer is designated as 44 in FIG. 7 and is deposited in a substantiallyconformal manner. The thin polysilicon layer 44 is preferably thickenough to reliably cover the topography presented by polysilicon layer36, vertical structures 42 and HSG-Si mask grains 40, and to provide agood quality conductor at the surface of the lower capacitor electrode.On the other hand, the polysilicon layer is kept thin so that the layer44 does not smooth the topography of the lower electrode too much and sothat the layer 44 does not fill the spaces between vertical structures42. To this end, it is preferred that the layer 44 is deposited to athickness of about 100-400 Å.

After the thin polysilicon layer 44 is deposited over the surface of thelower capacitor electrode, the lateral extent of the lower electrode isdefined by providing a photoresist mask over the polysilicon layer 44and etching the thin polysilicon layer 44 and etching the lower plate 36using, for example, a plasma etch using an etchant derived from HCl andHBr source gases. A capacitor dielectric layer 46 is then provided overthe surface of the thin polysilicon layer 44 and the edges of the lowerplate 36, as shown in FIG. 7. Various capacitor dielectrics are knownand include, for example, the multilayer oxide/nitride/oxide dielectrictypically referred to as "ONO." Such a structure may be formed byallowing a native oxide layer to grow over the rugged polysiliconsurface, depositing a thin layer of silicon nitride by chemical vapordeposition and then oxidizing a thin portion of the nitride surface in athermal oxidation process to complete the ONO capacitor dielectric 46.More preferably, the lowest oxide layer of the ONO structure issuppressed to form an "NO" capacitor dielectric. Still more preferableis the use of a higher dielectric constant material such as Ta₂ O₅ orone of the perovskite dielectrics such as barium strontium titanate.Next, an upper capacitor electrode 50 is formed over the bottomcapacitor electrode by blanket LPCVD of polysilicon, preferably doped insitu during deposition or by ion implantation and annealing. The uppercapacitor electrode 50 is patterned and further processing is performedto complete the DRAM device.

FIG. 8 shows an alternate embodiment of a DRAM cell in accordance withpreferred embodiments of the present invention. The structure in FIG. 8differs from the FIG. 7 structure primarily in the use of a planarizedinterlayer dielectric 60 in the FIG. 8 DRAM cell. The structuralelements of the FIG. 8 DRAM cell are generally similar to those of theFIG. 7 DRAM cell and so the following discussion provides only a summaryof the process used for forming the FIG. 8 structure. After formation ofthe transfer FET and wiring lines of FIG. 1, manufacture of the FIG. 8DRAM cell proceeds by depositing a comparatively thick interlayerdielectric 60, which may include oxide or other insulators, over thesurface of the FIG. 1 device. The surface of the interlayer dielectric60 is then planarized, for example, using a chemical mechanicalpolishing (CMP) process. A via 62 is then defined through the planarizedinterlayer dielectric 60 to expose the source/drain region 22 which thelower capacitor lower electrode will contact.

A lower conductive plate is formed for the capacitor electrode,typically by LPCVD of approximately 1500-2500 Å of polysilicon and byusing either in situ doping during deposition or ion implantationfollowed by a subsequent annealing step. If desired, the surface of theplate 64 may be planarized using CMP. Next, a thick oxide layer, similarto layer 38 of FIG. 4, is deposited over the surface of the polysiliconplate 64. Hemispherical grained polysilicon 66 is then deposited overthe surface of the thick oxide layer, in a manner similar to thatillustrated in FIG. 5. Anisotropic etching of the thick oxide layer isperformed using the HSG-Si grains 66 as a mask and an etchant derived ina plasma process from a fluorine-bearing source gas to form verticalstructures 68 extending from the surface of the polysilicon plate 64 tothe grains 66 of the HSG-Si mask. Processing proceeds by forming a thin,conductive polysilicon layer 70 over the topography of the lowerelectrode. The lateral extent of the lower capacitor electrode is thendefined using photolithography. A capacitor dielectric 72 is providedover the lower electrode and an upper capacitor electrode 74 is formedin the manner discussed above. The FIG. 8 structure and the process ofmaking the FIG. 8 structure have the advantage of greater processlatitude than is enjoyed by the FIG. 7 structure, because there is lesstopography to accommodate in the masking and etching steps of the FIG. 8manufacturing process.

While the present invention has been described in terms of certainpreferred embodiments thereof, those of ordinary skill in the art willappreciate that various modifications might be made to the embodimentsdescribed herein without altering the fundamental teachings of thepresent invention. As such, the present invention is not to be limitedto the particular specific embodiments described. Rather, the scope ofthe present invention is to be determined from the claims which follow.

What is claimed:
 1. A method of providing increased capacitance to acharge storage structure in an integrated circuit device, the methodcomprising:providing an access circuit in and on a substrate, the accesscircuit controlling access to an electrode of the charge storagestructure through an electrode contact; providing a first conductivelayer over the substrate and connected to the electrode contact;providing a layer of dielectric material over the first conductivelayer; providing a layer of grains of polysilicon over a surface of thelayer of dielectric material so as to leave uncovered portions of thesurface of the layer of dielectric material between the grains ofpolysilicon; selectively removing exposed portions of the layer ofdielectric material to form spaced apart columns of dielectric materialextending above the first conductive layer; providing a conformal secondconductive layer over the columns of dielectric material; providing acapacitor dielectric layer over the second conductive layer; andproviding a third conductive layer over the capacitor dielectric layer.2. The method of claim 1, wherein the access circuit comprises a fieldeffect transistor and the charge storage structure is in a DRAMcapacitor over bit line cell.
 3. The method of claim 2, wherein thefirst conductive layer is polysilicon deposited onto a planarizedsurface of a layer of oxide.
 4. The method of claim 1, wherein the firstconductive layer comprises polysilicon and wherein the selectivelyremoving stops on the first conductive layer.
 5. The method of claim 4,wherein the layer of dielectric material comprises an oxide or anitride.
 6. The method of claim 5, wherein the selectively removingincludes etching with an etchant derived from a fluorine bearing sourcegas.
 7. The method of claim 4, wherein the selectively removing uses thegrains of polysilicon as a mask for an etching process.
 8. The method ofclaim 7, wherein the grains of polysilicon have an average size ofbetween about 500-1000 Å.
 9. The method of claim 7, wherein the layer ofdielectric material comprises oxide and the selectively removingincludes etching with an etchant derived from a fluorine bearing sourcegas.
 10. The method of claim 7, wherein the second conductive layercomprises polysilicon deposited onto the grains of polysilicon, thecolumns of dielectric material and the first conductive layer.
 11. Themethod of claim 10, wherein the third conductive layer comprisespolysilicon.
 12. The method of claim 11, wherein the layer of dielectricmaterial comprises silicon oxide.
 13. A method of providing increasedcapacitance to a charge storage structure in an integrated circuitdevice, comprising:providing a field effect transistor on a substrate;the field effect transistor having a source/drain region; providing afirst dielectric layer over the field effect transistor and providing acontact via through the first dielectric layer to expose thesource/drain region; providing a first polysilicon layer over the firstdielectric layer and providing an electrical connection between thefirst polysilicon layer and the source/drain region; providing a seconddielectric layer over the first polysilicon layer; providing a layer ofhemispherical grained polysilicon over the second dielectric layer, thelayer of hemispherical grained polysilicon exposing portions of thesecond dielectric layer between grains of the layer of hemisphericalgrained polysilicon; anisotropically etching through the seconddielectric layer to expose portions of the first polysilicon layer in apattern defined by the grains of the layer of hemispherical grainedpolysilicon, structures etched from the second dielectric layerextending above the first polysilicon layer; depositing a secondpolysilicon layer over the exposed pattern of the first polysiliconlayer and over the structures etched from the second dielectric layer;providing a third dielectric layer over the second polysilicon layer;and providing a third polysilicon layer over the third dielectric layer,whereby a capacitive structure having two polysilicon layers separatedby the third dielectric layer is formed over the etched seconddielectric layer and in electrical contact with the portions of thefirst polysilicon layer exposed by the anisotropic etching.
 14. Themethod of claim 13, wherein the anisotropically etching uses the grainsof the layer of hemispherical grained polysilicon as a mask.
 15. Themethod of claim 14, wherein the second polysilicon layer is depositedover the grains of the layer of hemispherical grained polysilicon. 16.The method of claim 15, wherein the second dielectric layer comprisessilicon oxide.
 17. The method of claim 16, wherein the grains have anaverage size of between about 500-1000 Å.
 18. The method of claim 13,wherein the depositing of a second polysilicon layer includes depositinga conformal polysilicon layer over the exposed pattern of the firstpolysilicon layer and over the structures etched from the seconddielectric layer.
 19. A method of providing increased capacitance to acharge storage structure in an integrated circuit device,comprising:providing an access circuit in and on a substrate, the accesscircuit controlling access to an electrode of the charge storagestructure through an electrode contact; providing a first conductivelayer over the substrate and connected to the electrode contact;providing a layer of dielectric material over the first conductivelayer; providing a layer of grains of polysilicon over a surface of thelayer of dielectric material so as to leave uncovered portions of thesurface of the layer of dielectric material between the grains ofpolysilicon; selectively removing exposed portions of the layer ofdielectric material, leaving spaced apart columns of the dielectricmaterial extending above the first conductive layer beneath the grains,with portions of the first conductive layer exposed between the columns;providing a second conductive layer over the columns and the exposedportions of the first conductive layer; providing a capacitor dielectriclayer over the second conductive layer; and providing a third conductivelayer over the capacitor dielectric layer, whereby a capacitivestructure having two conductive layers separated by the capacitordielectric layer, is formed over the columns of the dielectric materialand in electrical contact with the first conductive layer between thecolumns.
 20. The method of claim 19, wherein the providing a secondconductive layer includes providing a conformal conductive layer overthe columns and the exposed portions of the first conductive layer.